 |  The Best of CDNLive: PCB Webinars
December 5-13Webinar Series for PCB Designers The Best of CDNLive: Custom IC Webinars
December11-12Webinar Series for Custom IC Designers Jack Benzel wins Nintendo WiiSeptember 12, 2007 2:30 pmJack won the drawing for the Nintendo Wii by being one of 71 attendees who responded to the 2007 Top Care-about surveys. This is Jack's second year as a presenter of technical paper and will definitely return next year. He felt the quality of papers was up from last year and he especially found the paper by Jayathi Subramanian of Freescale, "Performance Impact from Metal Fill Insertion" to be especially informative.
Jack's three teenagers were ecstatic when he text messaged to them that he had won the Wii.
Jack Benzel, Avago Technologies Manoj Gunwani remembers 3 big ideas from CDNLive!September 12, 2007 1:30 pmIn answer to the question, what ideas from CDNlive! made the most lasting impression, Manoj answered:
- Good to see more integrated comprehensive tools from Cadence
- Big push in Low-power tools and methodology
- System Verilog takes over in Verification
Manoj Gunwani, Principal engineer, IDT Sten Gustavson finds SPB 16.0 techtorial valuableSeptember 11, 2007 5:30 pmThe Sunday SPB back-end techtorial gave attendees enough time for hands-on in a semi-guided rather than rigid style. As a 20 year user of Cadence equipment I thought I was a dyed in the wool luddite, unable to change the interface I had been using for so long. Surprisingly, in about 30 minutes I decided, ok, this is a better way to go for most operations. So, if the purpose was to sell me, they succeeded. The last part of the techtorial dealt with user-defined constraints, showing us a very exciting change.
Sten Gustavson, PCB engineer, Cisco Harry Bartley finds discussion as informative as hands on demosSeptember 11, 2007 4:30 pmI attended the Sunday SPB front-end techtorial which was supposed to be four hours of hands-on demo. It ended up being four hours of discussion in a casual, question/answer format. Discussions with other Cadence users, Cadence architects and technical engineers provided me with a huge amount of usable information. To me this has been the high point of the event this year.
Harry Bartley, PCB engineer, Tektronix Randy Bye reviews SPB roadmap sessionSeptember 11, 2007 3:30 pmThe SPB Roadmap session was quite detailed through 2009 and beyond, not just high-level information. Presentations of future technology enhancements reflected the input users provided through the 2006 Top Care-about surveys with specific resposes to the requested technology enhancements. I was impressed by the speed of technology responses to the survey requests. I encourage all users to respond to the 2007 Top Care-about survey - Cadence listens.
Randy Bye, PCB forum moderator and Customer Advisory Team member, Unisys George Baird reviews keynotesSeptember 11, 2007 2:30 pmThe keynote speakers have been for me the best part of the event. Alberto was awesome. I appreciated his honesty on how difficult it will be when we begin parallel processing to help overcome some of the lower node technology challenges. Tom Reeves of IBM was quite insightful, discussing what they are doing with their technology. He shared some of their thoughts on what it is going to take to go below 35 nm, since we will be reaching that cap within the next year.
George Baird, RF Layout engineer, Broadcom Chris Day enjoys face-to-face communicationsSeptember 11, 2007 1:30 pmEvery year at CDNlive! I observe an interesting phenomenon - email is the number 1 form of communication, face-to-face is the least common form of communication yet is the most effective. This event is the only opportunity I have to meet face-to-face with other users. The face-to-face interaction is the reason I come to CDNLive! I can learn as much in the three days at CDNlive! as I do all year. The casual atmosphere promotes conversations - war stories trigger ideas to discuss.
Chris Day, Senior Solutions Engineer within the Motorola Engineering Tools and Solutions (METS) organization Functional Verification Roadmap review from Ross WeberSeptember 10, 2007 10:30 pmMonday 10:50am-11:35am Functional Verification Roadmap Steve Glazer presenting
I was pleasantly surprised to hear about many new technologies and features on the Cadence Functional Verification roadmap. Many of these new advancements are in direct response to the challenges and features that came out of the customer surveys from last year. It is great to see that Cadence is listening to what the customers are saying and responding quickly.
There were many exciting new features announced including the following:
- The Open Verification Methodology (OVM), a collaborative (Cadence and Mentor), class-based, open source, SystemVerilog library and methodology. This announcement was made previously, but is a great example of EDA vendors quickly answering the call of customers.
- UniCov, a new unified coverage database/tool along with the mention of a possible SQL database in the 2008 timeframe.
- Simulation and acceleration hot-swap capability offering users push-button capability of switching between simulation and acceleration in the same test. Coming later this year.
- High-speed formal analysis and hybrid ABV later this year.
Fill out the surveys this year, there are people listening on the other end!
Ross
Ross Weber, Unisys, Incisive Forum Moderator and Customer Advisory Team member Sufia Salim is at CDNLive! to meet the Cadence architectsSeptember 10, 2007 4:30 pmI attended the techtorials and am attending CDNLive! to meet the tool architects in person to discuss tool issues. I'm looking forward to seeing new directions we can take analog in the PCB area and fine-tune our environment
Sufia Salim, PCB Support, Analog Devices Sotirios Zogopoulos met a fellow Greek at the Networking LuncheonSeptember 10, 2007 2:00 pmAt the Verification Planning round table, Sotirious "put his design pain out in the open". He received great feedback on his planning process and made new contacts that will enable him to follow up with an sit down later to modify his own plan. During the nearly one hour conversation with other Verification Planning engineers, Sotirious and Stylianos discovered they are both native born Greeks living in the US.
Sotirios Zogopoulos, Aeluiros, Inc. Comment on Networking Luncheon by Stylianos DiamantidisSeptember 10, 2007 1:30 pmAs host for the Verification Planning round table today at the CDNLive! Networking luncheon I had the opportunity to meet people that I have talked to on the phone and worked with on projects over the years, but had never met face to face.
We talked about Verification Planning for over an hour; talking about different problem areas, such as physical verification. I was able to explore their perspective into the planning process - valuable information to have.
Stylianos Diamantidis, Globetech Solutions, Verification forum moderator and Customer Advisory Team member Welcome to CDNLive! SV 2007 from Mike CatramboneSeptember 10, 2007 8:15 amAs you know, CDNLive! Silicon Valley is happening this week. For those of you unable to attend, the user community will feature interviews and commentary from the event, so come back each day to find out what is happening.
This week we are also launching our second annual user community "Top Care-about Surveys" prepared by your forum moderators and their Customer Advisory Teams. These surveys are designed to capture users' top design challenges, and recommendations to Cadence on how to enhance the technologies to meet these challenges. We need your input, so please take the time to complete them
Survey results will be incorporated into Cadence roadmap sessions at CDNLive EMEA in 2008.
Results of the first annual survey are included in the roadmap sessions at CDNLive! SV this week
Enjoy a great conference
Mike Catrambone, Chairman, Cadence Designer NetworkPlan-to-closure techtorial coverage from Ross WeberSeptember 9, 2007 6:00 pmSunday, 9am-1pm, Techtorial 1: Design with Verification Featuring the Incisive Plan-to-Closure Methodology with Assertions and Module-Based SystemVerilog. Ben Ting and Tim Pylant presenting.
The first half of the presentation featured an excellent overview of ABV integrated into Cadence's Incisive Plan to Closure Methodology (IPCM) by Ben. Particularly focusing on the relationship of checkers and coverage to the verfication plan, how the checkers and coverage are implemented, and how they are verified in both dynamic and formal verification environments. In the second half Tim Pylant, a SystemVerilog and URM guru, provide expert explanations of many of the new constructs introduced with SystemVerilog and further explained how URM takes advantage of the SystemVerilog features. Both halves of the techtorial were filled with interesting questions and discussions from the audience of about 15-20. The slide packets we received are going to be great reference materials.
Content-wise it was a great start to my third CDNLive experience.
Ross Weber, Unisys, Incisive Forum Moderator and Customer Advisory Team member | |
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