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| Many features built into the SystemVerilog language make it ideal as a high-level verification language. Using class libraries with SystemVerilog can take this a step further by enhancing productivity and enabling better, more efficient reuse between engineers and between projects. The Verification Methodology Manual (VMM) class library was one of the first SystemVerilog class libraries available, and has been widely adopted. The Universal Reuse Methodology (URM) class library has more recently become available, and while it is similar to VMM in many respects, there are also some important differences. This paper, voted the Most Valuable Paper at CDNLive! Silicon Valley 2007, describes the process of converting an existing testbench based on VMM class libraries to one based on URM class libraries. It highlights which aspects of the conversion were straightforward and which aspects required more attention. The session concludes by summarizing the similarities and differences between the two approaches, and any potential advantages achieved by doing the conversion
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| | Translation of an Existing VMM Testbench into URM »
Translation of an Existing VMM Testbench into URM, Powerpoint Presentation »
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About the author
Kelly Larson is the verification manager for the DSP group at Analog Devices in Austin, Texas, where he joined in 2000. Kelly and his group do verification of DSP processor cores for ADI’s Blackfin architecture, as well as SOC’s for wireless, automotive, video and general purpose applications. Prior to moving to Texas, he worked in the processor design group at Hewlett-Packard in Fort Collins, Colorado. Kelly has worked in the area of functional verification for over 16 years. He holds a BS degree in Electrical Engineering from Brigham Young University, and an MS degree in Electrical Engineering from the University of Colorado at Boulder. |
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